Solar cells are typically manufactured using the same processes used for other semiconductor devices, often using silicon as the substrate material. A semiconductor solar cell is a device having an in-built electric field that separates the charge carriers generated through the absorption of photons in the semiconductor material. This electric-field is typically created through the formation of a p-n junction (diode) which is created by differential doping of the semiconductor material. Doping a part of the semiconductor substrate (e.g. surface region) with impurities of opposite polarity forms a p-n junction that may be used as a photovoltaic device converting light into electricity.
FIG. 1 shows a cross section of a representative substrate 100, comprising a solar cell. Photons 101 enter the solar cell 100 through the top surface 105, as signified by the arrows. These photons pass through an anti-reflective coating 110, designed to maximize the number of photons that penetrate the substrate 100 and minimize those that are reflected away from the substrate.
Internally, the substrate 100 is formed so as to have a p-n junction 120. This junction is shown as being substantially parallel to the top surface 105 of the substrate 100 although there are other implementations where the junction may not be parallel to the surface. The solar cell is fabricated such that the photons enter the substrate through the n-doped region, also known as the emitter 130. While this disclosure describes p-type bases and n-type emitters, n-type bases and p-type emitters can also be used to produce solar cells and are within the scope of the disclosure. The photons with sufficient energy (above the bandgap of the semiconductor) are able to promote an electron within the semiconductor material's valence band to the conduction band. Associated with this free electron is a corresponding positively charged hole in the valence band. In order to generate a photocurrent that can drive an external load, these electron-hole (e-h) pairs need to be separated. This is done through the built-in electric field at the p-n junction. Thus any e-h pairs that are generated in the depletion region of the p-n junction get separated, as are any other minority carriers that diffuse to the depletion region of the device. Since a majority of the incident photons are absorbed in near surface regions of the device, the minority carriers generated in the emitter need to diffuse across the depth of the emitter to reach the depletion region and get swept across to the other side. Thus to maximize the collection of photo-generated current and minimize the chances of carrier recombination in the emitter, it is preferable to have the emitter region 130 be very shallow.
Some photons pass through the emitter region 130 and enter the base 140. These photons can then excite electrons within the base 140, which are free to move into the emitter region 130, while the associated holes remain in the base 140. As a result of the charge separation caused by the presence of this p-n junction, the extra carriers (electrons and holes) generated by the photons can then be used to drive an external load to complete the circuit.
By externally connecting the emitter region 130 to the base 140 through an external load, it is possible to conduct current and therefore provide power. To achieve this, contacts 150, typically metallic, are placed on the outer surface of the emitter region 130 and the base 140. Since the base 140 does not receive the photons directly, typically its contact 150b is placed along the entire outer surface. In contrast, the outer surface of the emitter region 130 receives photons and therefore cannot be completely covered with contacts. However, if the electrons have to travel great distances to the contact, the series resistance of the cell increases, which lowers the power output. In an attempt to balance these two considerations; the distance that the free electrons must travel to the contact, and the amount of exposed emitter surface 160; most applications use contacts 150a that are in the form of fingers. FIG. 2 shows a top view of the solar cell of FIG. 1. The contacts are typically formed so as to be relatively thin, while extending the width of the solar cell. In this way, free electrons need not travel great distances, but much of the outer surface of the emitter is exposed to the photons. Typical contact fingers 150a on the front side of the wafer are between 40 μm and 200 μm. These fingers 150a are typically spaced between 2-3 mm apart from one another. While these dimensions are typical, other dimensions are possible and contemplated herein.
A further enhancement to solar cells is the addition of heavily doped substrate contact regions. FIG. 3 shows a cross section of this enhanced solar cell. The cell is as described above in connection with FIG. 1, but includes heavily n-doped contact regions 170. These heavily doped contact regions 170 correspond to the areas where the metallic fingers 150a will be affixed to the substrate 100. The introduction of these heavily doped contact regions 170 allows much better contact between the substrate 100 and the metallic fingers 150a and significantly lowers the series resistance of the cell. This pattern of including heavily doped regions on the surface of the substrate is commonly referred to as selective emitter design. These heavily doped regions may be created by implanting ions in these regions. Thus, the terms “implanted region” and “doped region” may be used interchangeably throughout this disclosure.
A selective emitter design for a solar cell also has the advantage of higher efficiency cells due to reduced minority carrier losses through recombination due to lower dopant/impurity dose in the exposed regions of the emitter layer. The higher doping under the contact regions provides a field that collects the majority carriers generated in the emitter and repels the excess minority carriers back toward the p-n junction.
In addition to selective emitter designs, other solar cell designs require patterned doping. Another example is the interdigitated back contact (IBC) cell, which requires offset patterns of n-type and p-type dopants on the back side of the cell.
Such structures are typically made using traditional lithography (or hard masks) and thermal diffusion. An alternative is to use implantation in conjunction with a traditional lithographic mask, which can then be removed easily before dopant activation. Yet another alternative is to use a shadow mask or stencil mask in the implanter to define the highly doped areas for the contacts. All of these techniques utilize a fixed masking layer (either directly on the substrate or in the beamline).
All of these alternatives have significant drawbacks. For example, the processes enumerated above all contain multiple process steps. This causes the cost of the manufacturing process to be prohibitive and may increase wafer breakage rates. These options also suffer from the limitations associated with the special handling of solar wafers, such as aligning the mask with the substrate and the cross contamination with materials that are dispersed from the mask during ion implantation.
FIG. 4 shows the typical processing steps required to create patterned doping using a shadow or proximity mask. In step 400, the solar cell is designed. This includes creating the dopant patterns and metallization layers. Based on the desired dopant patterns, a matching proximity mask is design (step 410). Pre-implant manufacturing processes are performed (step 420). For example, in some embodiments, the wafers arrive at the factory as raw sawn wafers. The first step on entering the factory is inspection. The wafers are checked for cracks, resistivity & size. After that, the wafer may go into a series of wet benches. The first wet step may be to remove the saw damage from the wafers. This is typically a 10 um etch from both sides of the wafer to remove the micro-cracks formed by sawing. The next step may be an anisotropic etch that forms the random pyramid texturing on the wafer surfaces. This may help light trapping. The pre-processed wafer is then physically aligned within the ion implanter (step 430). This step also includes precise positioning of the proximity mask. The ion implant of the wafer is then performed, with the proximity mask in place (step 440). After the wafer has been implanted, various post-processing steps, such as anneal and SiNx deposition, are performed on it (step 450). The wafer is aligned with respect to a reference edge or indicia prior to application of the metallization pattern (step 460). Finally, the metal layer is applied to the wafer (step 470). In the case of a solar cell, the metal layer is typically applied atop the heavily doped regions of the wafer (i.e. those regions implanted during implantation step 440). The final step of fabricating a solar cell is the firing step, where the printed metal is driven in to the cell to make the actual contacts.
However, there are many known problems with the use of a proximity mask, especially in solar cell applications. FIG. 5 shows a wafer 501 being implanted by an ion beam 502, through a proximity mask 503. The mask 503 has a plurality of slots, where each is separated from the adjacent slots by a slot-location spacing 500. The first of these slots is offset from an indicia 504 by a distance 510. The mask 503 has a certain thickness (t) and is offset vertically above the wafer 501 by a gap. As shown in FIG. 5, the ion beam 502 may not be completely orthogonal to the wafer 501. The beam angle (θ), the mask thickness (t) and the gap from the mask 503 to the wafer 501 all have an effect on the location of the implanted regions 505. For example, the greater the gap between the mask 503 and the wafer 501, the more lateral displacement between the desired implant region and the actual implant region 505. Similarly, a thicker mask will tend to reduce the overall width of the implanted region 505, to a width less than the slot width 520. In addition, the use of a proximity mask 503 requires multiple alignment steps. First, the mask 503 must be aligned with the wafer 501. Subsequently, the metal layer has to be aligned as well. FIG. 5 shows the metal 506 applied in the desired location. However, the variability of the steps creates a situation where the metal 506 is not applied over the center of the implanted region 505. The offset from the implanted region 505 to the metal 506 is referred to as feature error, and is shown as being positive on the left side of the implanted region 505 and negative on the right side of the implanted region 505.
In summary, proximity masks can cause the following problems:                Variability of desired feature placement due to machining tolerances;        Variability of feature placement due to incident ion beam angle accuracy (resulting from mask gap or ion beam repeatability);        Variability of feature placement due to wafer positioning;        Variability of feature placement due to wafer size tolerances; and        Tight alignment requirement for the application of metallization.        
To accommodate these system tolerances, often the implanted region 505 is larger in size than optimally desired. In the case of selective emitter cells, the oversized implanted regions 505 expand into the emitter region, thereby reducing the surface area of the emitter region. This results in a lower cell efficiency.
FIGS. 6A-C show the impact of these wider implanted regions on a solar cell 600. FIG. 6A shows a typically geometry of a solar cell with busbars 605 and metal fingers 610. FIG. 6B is an expanded view of a portion of FIG. 6A, showing the metal fingers 610, busbar 605 and implanted regions 615 in more detail. To insure that the metal fingers 610 and busbars 605 do not cover the emitter region 620, the implanted regions 615 are created with a greater width than desired. Note that any area which is implanted and not covered by metal is less efficient in capturing solar energy.
FIG. 6C shows a section view of an existing process. The metal finger 610 is located at the leftmost position, based on known tolerances. To insure that the metal finger 610 does not contact the emitter region 620, the implanted region 615 is made wide enough such that in all scenarios, with maximum tolerances and minimum widths, the metal finger is covering only implanted region 615. However, the exposed portions of implanted region 615 are less efficient in capturing solar energy.
In addition, high precision alignment systems and the above described production method is inherently costly. Consequently, efforts have been made to reduce the cost and effort required to dope a pattern onto a solar cell.
Therefore, there exists a need to produce solar cells where the number and complexity of the process steps is reduced, while maintaining adequate accuracy so that subsequent process steps are correctly positioned. While applicable to solar cells, the techniques described herein are applicable to other doping applications.